D. Scott Wills and Joseph L.A. Hughes
School of Electrical and Computer Engineering
Georgia Institute of Technology
Atlanta, Georgia 30332-0250
The first two courses provide a common core for both EE and CmpE majors. The first course introduces the design hierarchy, beginning with CMOS switches. Gate, building block, and microarchitecture levels of the hierarchy are introduced with an emphasis on abstraction and protocols between layers. The second course introduces instruction set architectures and examines implementation trade-offs. A RISC microprocessor implementation (MIPS) provides a concrete example for more abstract design tradeoffs. The third and fourth courses, taken by all CmpE and some EE majors, provide advanced material in the architecture and digital design areas including pipelining, advanced memory system design, digital logic synthesis, synchronous and asynchronous sequential system design trade-offs, and clocking schemes. These courses emphasize actual implementation trade-offs rather than relying on the idealized models typically used in lower-level courses.
Because of rapid advances in digital technology, including integrated circuits and high-performance microprocessors, new electrical and computer engineering graduates need vastly different skills and knowledge than those who graduated just a few years ago. Elements of digital logic design, computer architecture, and programming have combined into the more complex area of digital computation. Key concepts include hierarchical modular design, system-level trade-offs, and computer-based design and analysis tools. To properly prepare students for this new environment, traditional course in these disciplines must be re-thought.
This paper describes a new digital computation sequence introduced at Georgia Tech during the past two years as part of a major restructuring of the Computer Engineering degree program. This four-course core sequence integrates elements of digital design, computer architecture, and system specification in a systems-oriented presentation, rather than presenting them as independent topics. Real-world design environment tools for digital logic design and simulation, instruction-level simulation, and VHDL-based architectural modeling complement hands-on hardware implementation laboratories. Each course lasts for one quarter, with approximately 25 lecture hours.
The first course introduces the design hierarchy, beginning with CMOS switches. Gate, building block, and microarchitecture levels of the hierarchy are introduced with an emphasis on abstraction and protocols between layers. State machines are introduced to complete a basic sequential computer. The second course introduces instruction set architectures and examines implementation trade-offs. A RISC microprocessor implementation (MIPS) provides a concrete example for more abstract design tradeoffs. Tightly coupled laboratories and computer-based assignments consolidate key concepts. The first two courses provide a common core for both EE and CmpE majors. The third and fourth courses provide advanced material in the architecture and digital design areas including pipelining, advanced memory system design, digital logic synthesis, synchronous and asynchronous sequential system design trade-offs, and clocking schemes. These courses emphasize actual implementation trade-offs rather than relying on idealized models typically used in lower-level courses. All CmpE majors take both of the advanced courses along with EE majors specializing in related areas.
This integrated course sequence provides a system-oriented, tool-driven foundation for today's electrical and computer engineers. Coordination between lectures and laboratory experiences (both structured and independent) enhances understanding of the material by providing hands-on applications. The following sections outline the four core courses in this sequence. The final section describes the relationship of this course to other classes in the curriculum.
The first course in the sequence introduces the fundamental concepts of digital computation. It is taken in the freshman year, and is typically the first course in the major for EE and CmpE students. The only prerequisite is computer use, so knowledge of circuits and programming concepts cannot be assumed. This leaves two alternatives: build on the engineering students' strong mathematical background or on their intuition. The former approach is more common in introductory digital design courses: begin with number systems, then Boolean algebra, and then gate abstraction. A superficial summary of a gate implementation technology (e.g., TTL) may be included in the text, although such sections are often skipped because of the students' lack of preparation.
We chose the latter approach of building upon students' intuitive understanding of simple switching circuits. In this approach, digital computation begins with basic switching circuits (e.g., serial switches imply ``AND;'' parallel switches imply ``OR)''. Ideal level-activated switches (nFETs and pFETs) are introduced and design techniques for realizing combinational functions are presented. Boolean algebra is presented in terms of switching circuits. The goal of this approach is to provide an intuitive presentation of combinational logic through design-oriented examples. Fundamental principles like de Morgan's Theorem are illustrated through design problems (e.g., design the dual nFET network for a given pFET network).
It is interesting to note that this focus on logic-controlled switches as the fundamental element is not new, but was used in early digital logic design courses. The difference is the change in implementation technology from relays to MOSFETs. (Many older textbooks refer to ``switching theory'' rather than ``logic design'' in their titles.) Since then, the focus on logic gates as the fundamental digital building block reflected the prevalence of SSI and MSI chips used for printed circuit board designs. With silicon VLSI as the implementation technology for most digital systems built today, EE and CmpE students require a basic understanding of the technology in order to appreciate the rapid advances in digital computation. However, courses on VLSI design are typically advanced electives taken by students who want to learn how to build integrated circuits.
Switch-level design forms the bottom layer of the digital system hierarchy that extends throughout the core course sequence. Since students begin this sequence in their freshman year, their lack of electronics background allows only basic concepts of parametric operation (e.g., propagation delay, fanout and loading). When sequential circuits are introduced, a two-phase non-overlapping clocking scheme is introduced to generalize clock cycles while avoiding complexities of race conditions, glitches, etc. (These topics are covered in the advanced digital computation class.) Level-sensitive storage devices are used for most exercises, although edge-triggered devices also are introduced. The evolution begins with the RS latch, then the transparent D latch, then shift registers, and finally full multi-ported registers. Flip flops (D, JK, etc.) are introduced with counters later in the course.
At this stage, binary number systems and arithmetic are introduced, along with functional units such as adders, logical units, and shifters. Trade-offs in function implementation are explored (e.g., restoring gates versus pass gates). By understanding the switch level, students can assess design tradeoffs in tangible metrics, namely number of switches. Finally, all material is brought together in the design of an elementary data path consisting of a register file and several functional units that form a simple three-bus microarchitecture. A state machine provides control for computing arithmetic expressions (e.g., a specified polynomial). Memory arrays also are introduced.
The class is paralleled by weekly laboratories which include both computer-based and hardware-based exercises. LogicWorks and spot tools, such as espresso for logic equation minimization, are used to design several systems. Table 1 gives an outline of the digital computation course.
The second core course expands the digital computation hierarchy to include computer architecture. This course follows the RISC processor development in Computer Organization &Design, The Hardware/Software Interface by David Patterson and John Hennessy. In this course, system performance metrics are defined and an instruction set architecture is specified (MIPS R2000). A design-oriented study of processor architecture development build on elements from the digital computation course. Assignments in MIPS assembly language prepare for future courses in programming, compilers, and operating systems. The course outline is given in Table 2.
Weekly laboratories incorporate specification and simulation of processor architectures in VHDL. Elements of the MIPS R2000 architecture presented in class are mirrored in laboratory projects. Programmable logic devices provide hands-on debugging and analysis of modules designed in VHDL.
The first two core courses provide a baseline understanding of digital computation and computer architecture. EE students who are concentrating in areas not directly connected to digital computation and computer architecture (e.g., electromagnetics or power systems) can leave this sequence with reasonable understanding of this material, plus a general introduction to problem solving and system design. While the specifics of the design hierarchy vary from discipline to discipline, these classes introduce concepts common to all engineering design.
The two remaining core courses parallel the introductory courses, with one focusing on digital computation and one focusing on computer architecture. These courses require both of the earlier courses as prerequisites, but are independent of each other. This allows EE majors to take the courses separately as preparation for advanced electives in computer architecture, VLSI design, signal processing, and related areas.
The second digital computation course plays a key role in the revised computer engineering curriculum. Positioned in the middle of the junior year, it draws together earlier coursework in digital design, computer architecture, and analog electronics. Similarly, the laboratory provides a transition from the ``cookbook'' experiments of earlier courses to the open-ended design projects associated with senior electives and the 2-quarter CmpE major design sequence. The primary emphasis of this course is on the design trade-offs associated with practical digital systems. Inherent in this is an acknowledgment that life-cycle costing involves many factors that are not easily quantified and which may interact in complex ways.
The topical outline for this course is given in Table 3. Whereas the first core course covers logic minimization (gate count) with methods such as Karnaugh maps and espresso, this course emphasizes logic optimization matched to specific implementation requirements. Thus, wiring complexity or gate fan-in may be more critical measures for a specific design problem. Similarly, the design of sequential systems focuses on implementation options rather than just functional correctness.
The first course in computer architecture presented approaches to realizing the functionality of a modern computer; the advanced course emphasizes the performance of a computer. Pipelining techniques are introduced to improve instruction throughput; data and control hazards are explained and solutions are presented. The memory system is significantly refined to include caches, interleaved memory, and virtual memory. Performance and cost are considered for each technique. Laboratories for this course include advanced VHDL projects related to concepts covered in class. Simulations are used to gauge the realized performance improvement as well as the increased realization costs. The course outline is given in Table 4.
The four-course core sequence in digital computation and computer architecture described in this paper was developed to address three key issues: integration of digital logic design and computer architecture, hierarchical and modular design with an emphasis on system-level issues, and the use of computer-based tools for design and analysis. This restructuring of the traditional digital logic and computer architecture courses reflects ongoing trends in digital system technologies and design methods, ensuring that students are properly prepared. Overall, this new sequence provides greater emphasis on architectural design and less hands-on experience in gate-level digital logic design and assembly language programming, particularly for EE students who take only the first two courses.
It should be noted that the an earlier version of the revised core sequence proposed more significant changes in two areas: (1) greater integration of digital logic design with architectural design and (2) a top-down approach, starting with system-level design and specification rather than the low-level digital building blocks. While there was substantial support for this model for CmpE majors, practical considerations (such as availability of textbooks, EE majors taking only two of the four courses, and course compatibility for transfer students) resulted in the version described in this paper.
The first groups of students are just now completing the full four-course sequence, so it is too early to evaluate whether or not they will demonstrate better performance in their senior-level design courses. However, the inclusion of certain advanced concepts in the revised core courses allows more time in the senior-level courses for additional topics and longer design projects, a significant improvement given the time limitations of the quarter schedule.
