Anthony J. A. Oxtoby, Associate Professor, EET Department, Purdue University
Waveform generation is extended to include generation of an waveform derived from an automobile engine speed sensor, FIR filtering is extended into x8 output oversampling of audio signals and the IIR filter is extended to a 6 band graphical audio equaliser. Elements of hardware interfacing through the processor's high speed serial ports (SPORTs) are also included.
Developments in VLSI technology over the last 15 years have resulted in the availability of economical yet powerful processors designed specifically to efficiently implement the kernel arithmetic operation of forming the sum of products which is associated with common digital signal processing activities such as spectral estimation and filtering. The areas of application of this technology have likewise shown phenominal expansion with an associated rapid growth in the availablity of hardware and software development tools.
Here in the EET department at Purdue University, there has been a gradual increase in activity in this area at the graduate level over the past three years which has fostered the development of a 4 credit hour undergraduate junior/senior level course in Real-Time DSP which, whilst currently offered as an elective, will become a required course in the Spring of 1997 as part of a newly revised curriculum.
This course aims to develop the student's understanding of the fundamental concepts, language and some applications of discrete time signal processing whilst also providing the experience of working with a modern general purpose DSP processor.
The course pre-requisites include a working knowledge of the architecture and software development tools (assembler and linker) associated with a general purpose microprocessor and also familiarity with MSDOS and EXCEL. In addition a knowledge of linear system concepts is required including Laplace transforms, poles and zeros, transfer functions, frequency response, impulse response, linear filter approximations e.q. Butterworth, Chebyshev I and II and Fourier series. An understanding of the solution of linear constant coefficient differential equations and of power series is also required.
The course introduction describes the essential features of a DSP system and outlines some simple applications to highlight the key sum-of-products operation and then relates this to the architecture and instruction set features found in general purpose DSP processors as exemplified in the ADSP2101 processor. This is then followed by a section on the fundamental properties of discrete time signals, aliasing and its impact on the sampling rate and real-time algorithms. Antialias filter characteristics are then covered as is oversampling, decimation. and the signal reconstruction process. Properties of LTI systems are then reviewed. Difference equations are introduced along with the concept of the unit time delay and finally block diagram representations of difference equations. The course then continues with linear convolution and formal coverage of the z transform representation of discrete sequences.
Digital filters are covered next with accent on IIR and FIR filters and their characteristics, differences and relative advantages and disadvantages. The course then takes a closer look at FIR filters and their structure, specifications and design methods with the focus on the Fourier series and equiripple design methods. Design tradeoffs beween filter performance specs. and design parameters are highlighted. Recursive filters are covered next commencing with a brief review of analog filter design based on Butterworth, Chebyshev and other low pass prototypes and frequency transformations. S plane to z plane mapping is then introduced and various methods compared and the need for prewarping demonstrated but emphasis is placed on the use of the bilinear transformation. Practical implementation considerations are then introduced such as the effects of filter coefficient truncation on pole positions, and its impact on the choice of filter structure. Input signal and coefficient scaling for filter implementation on a fixed point arithmetic processor is also covered.
Finally the Fourier series is reviewed and extended to the Fourier transform. The discrete Fourier transform is considered along with the need for windowing and a comparison of window functions. Emphasis is placed on understanding the fundamentals of implementation and the uses and results of the DFT. The computational inefficiency of the DFT is discussed and leads to the introduction of the FFT.
DSP experiments and projects are conducted in the microprocessor laboratory. Sixteen of 36 stations are each equipped with a 486 based PC with 12Mbyte of RAM together with a DC supply, oscilloscope, and programmable function generator to service courses in DSP and PLDs. Laboratory experiments are largely designed around the Analog Devices ADSP2101 16 bit fixed point 12.5 MHz. processor with 2kwords of 24 bit program memory (PM) and 1kwords of 16 bit data memory (DM), both on chip. Thus each station also has an ADSP2101 based EZ-LAB [1] hardware platform together with an EZ-ICE [2] in circuit emulator.
The various processor specific software development tools consisting of an ANSI C compiler, assembler, linker, system builder for creating the hardware architecture description files, PROM splitter, simulator and finally the debugging and PC to EZ-ICE communication software are all installed on the PC which, in turn, is linked to the EZ-ICE via an RS232 serial port.
Executable code can be debugged and run in non-real time on the PC using the ADSP2101 simulator which has features for importing from or exporting to external data files to simulate I/O data transfer. The simulator can also display memory contents and I/O data graphically. Alternatively code can be downloaded to the EZ-ICE, which is usually plugged into the EZ-LAB, and then run in real time with access to external signals and test equipment via the EZ-LAB I/O features. Code can also be examined and debugged in the EZ-ICE emulator environment by making use of the window displays of program and data memory content, and the contents of the various computational, status and control units which make up the processor. Single step, multiple step and breakpoint features are also available.
All real time code execution and interfacing lab activities are implemented on the ADSP2101 EZ-LAB hardware with the associated EZ-ICE. The EZ-LAB consists of a 12.5MHz. processor together with an 8 page 64 kbyte x 8 bit external boot EPROM containing demonstration programs. A single channel of analog I/O interfacing is implemented through one of the processor's high speed serial ports (SPORTS) via a CODEC designed for voice band signals in the 300Hz. to 3500Hz. range and operated at a sampling rate of 8kHz. The CODEC is buffered on it's analog input with a single, variable gain, non-inverting op-amp circuit and followed on the analog output by a variable gain 1.5W power amplifier.
In addition a 4 channel double buffered 8 bit DAC is mapped onto the data memory data bus of the processor. However the DAC is only partially address decoded.
Connection of additional application specific hardware to the processor is made through the two high speed synchronous serial ports available on the ADSP2101 processor or mapped into the processor's data memory via the bus and control lines available through a 60 way connector.
Normally the ADSP2101 processor on the EZ-LAB is removed and the EZ-ICE emulator is plugged into the processor socket to allow code to be downloaded from the PC to the emulating ADSP2101 and then executed in real time with the I/O hardware. Although most code can be implemented with the standard 2k PM and 1k DM the EZ-ICE has 8k of 24 bit wide overlay memory which can be used as PM, DM or a mixture of both with the memory segmentation being determined by the user.
The ADSP2101 based hardware was chosen since it is a free standing unit rather than a PC plug-in board so that the hardware is very accessible for students and thus permits easy interfacing of external breadboard circuitry. At the time of selection it was also competitively priced for universities, however more recent offerings from TI and Motorola have removed any price advantage. In addition, the assembly language instruction set is relatively high level, and many instructions can be almost intuitively understood. This has proved to be a singular advantage in this introductory course.
In addition to the processor specific software development tools listed above, a PC based software package used to implement more general DSP operations such as FIR and IIR filter design and analysis, linear convolution, correlation and DFT and FFT spectral estimation along with fundamental generation and manipulation of discrete time signals has been adopted.
The PCDSP [3] package was selected since it is easy to use, menu driven, inexpensive and requires a minimal platform to run on i.e. 286 machine with MSDOS ver. 3.0 and 640k of RAM.
This software is particularly useful for digital filter analysis and design. Also in lookup table waveform generation and FIR filter implementation the generation and manipulation of large numbers of coefficients which must be stored in the processor's memory is performed easily. Coefficients generated on PCDSP are saved to an ASCII file and then converted into 1.15 fractional HEX numbers through a program called HEXCON written by the author. The HEX data is then initialised into appropriate PM or DM locations along with the DSP source code during the linking process.
Wherever possible use is also made of EXCEL spreadsheet software. For example the recursive equation associated with the digital sinewave generator is implemented and the waveform plotted for different coefficients and initial conditions. Also various window functions and the final coefficients of FIR filters designed using the Fourier series method can easily be generated on the spreadsheet. Biquad IIR filter design is also implemented on the spreadsheet. Thus student's are forced to work with basic equations associated with DSP operations and applications but can use, and appreciate, the power of the spreadsheet to solve these equations, graphically display results and quickly implement design changes and `what if' investigations whilst avoiding the tedium of repetitive calculations.
The philosophy adopted in the design of the laboratory exercises has been to expose the student to a range of common DSP operations and applications such as waveform generation, filtering and spectral estimation, but in addition to then extend those concepts into useful applications chosen to spark the student's interest and generate enthusiasm for working with the processor. Where appropriate mini lectures of 20 to 30 minutes are given at the start of the lab period to cover topics associated with the processor architecture, hardware, instruction set and code, all of which is written in assembly language.
The rest of this section shows the range of laboratory work covered and will describe in detail a few experiments and mini projects.
This is a relatively easy starter lab to introduce students to the mechanics of working with PCDSP and involves exercises in data entry, sequence generation and manipulation so that the PCDSP environment is explored.
In this exercise students work with two hardware devices - a sample and hold circuit, the SMP-11, and a 14 bit serial analog I/O chip, the AD7869. The phenomenon of aliasing is examined using each device in turn and the relationship between the sampling frequency, the input signal frequency and the frequencies of the aliases established. This exercise has the added benefit in that students gain familiarity with the AD7869 which they must interface to the ADSP2101 in a later project. A demonstration is also shown where a signal is sampled through an RTI815 PC based data acquisition card and aliases generated and displayed on the PC screen.
The objectve of this lab is to familiarise students with the various software tools used in development of ADSP2101 code. Generation of architecture description files, assembling, linking, loading and debugging an assembly language program which is supplied are all covered together with explanation of the contents of the various files produced at any stage. The program supplied samples a signal through the codec and then outputs it to an oscilloscope or a loudspeaker. The debugging features of the simulator and of the EZ-ICE software are also exercised.
This lab is performed entirely on the simulator and is designed to introduce students to processor instructions associated with the three main computational units, viz. the MAC, ALU and barrel shifter. It also demonstrates the difference between the fractional and integer arithmetic modes of operation of the MAC and introduces students to the various fractional binary number representations i.e.1.15, 2.14 etc.
This DSP application is frequently covered as an extension of IIR filtering since it is based on a zero input 2nd order IIR filter. In this course it is tied to waveform generation and the recursive solution of the difference equation obtained from the z transform of sin(n(T). Thus comparison can be made between the generation of a sequence using look up tables and using the compact form of the z transform expression which recusively generates the discrete sinewave sequence. The effect on the output waveform of changing the various coefficients and initial conditions is investigated and summarised by the student.
This experiment forms a prelude to the next two labs on FIR filtering. The objective here is to relate the time-reverse, multiply, integrate and shift operations associated with the linear convolution of an input signal with the impulse response of a LTI system to form the output signal, to the sequence of operations necessary to implement convolution on the processor. The key again is the use of the processor data address generators (DAGs) to update the input sampled data delay line located in a circular buffer in DM and also to sequentially fetch data into the multiply-accumulator (MAC) from the input sample data delay line, and from the PM circular buffer used to store the LTI system impulse response. The convolution code is initially implemented on the ADSP2101 simulator where students convolve various pairs of sequence patterns previously generated on PCDSP, converted to 16 bit HEX values and located in PM and DM during the linking process. A graphical display of the resulting output data is then obtained when the code is executed and compared to those predicted using PCDSP or from hand calculations. Finally a digital 1 pole low pass filter is designed using PCDSP and the associated impulse response coefficients are then truncated to 20 terms, converted to HEX, located in PM, and then convolved, in real time with a sinusoidal input from a generator. The overall frequency response is then measured and compared to that predicted using both PCDSP and the ADSP2101 simulator. This comparison is useful since the initial transient can be seen whereas only steady state behaviour is observed during the real-time execution.
This lab involves code development and execution
for a 2nd order IIR filter which is the digital equivalent of an underdamped
analog `ring of three' low pass filter with a
Q of 10,
Hz. and a sampling frequency of 8kHz. The design
is covered in the lecture where the transfer function of the digital filter
is established as:
Implementations using direct forms I and II are covered and students are shown how the use of the ADSP2101 DAGs and associated circular buffers together with multifunction instructions can lead to very efficient implementation of the IIR filter equations as was achieved for the FIR filter.
The problem of scaling to prevent overflow via input signal scaling and/or filter coefficient scaling is also considered. Again, EXCEL is very useful in importing the IIR impulse response data from PCDSP and then computing the scale factors to be applied based on which output signal estimate is adopted [7]. Actual and predicted (using PCDSP) frequency response behaviour are compared and students must fully explain their code operation and the process of filter design and implementation.
The work of lab#10 is now reinforced and extended by means of a short project, occupying 9 lab hours, in which a 6 band graphic equaliser based on Butterworth 2nd order filters is implemented by students working in pairs. This project involves filter design from a given set of specifications, the implementation of the algorithm and the interfacing of a high speed serial output 8 channel ADC and a 100kHz serial output ADC/DAC to the two ADSP2101 serial ports.
A structured approach to the project is enforced such that a single biquad filter is first designed and implemented and then extended to include variable gain. This is then extended to the design and implementation of multiple biquads each with appropriate centre frequencies and seperately controlled gains. Finally feedforward and master volume control is added. At all stages of development the measured behaviour must be confirmed by analysis performed using PCDSP.
The design of each biquad bandpass filter used in the equaliser is performed by programming the transformation equations into EXCEL. The grading for the project is based on a sliding scale depending on how many stages of development were successfully achieved. In addition individual students are regularly required to answer questions to test their understanding of the project solution. A final summary report is also required.
This paper has described some initiatives in the development of an undergraduate course in DSP at junior/senior level in a EET program. The course puts a heavy emphasis on the implementation, using a modern 16 bit fixed point processor, of some common DSP applications and extends these into identifiably useful applications. Student activity especially in the lab and general course feedback suggests that this approach provides powerful motivation for students to work with the processor and interface hardware. In addition the early introduction of lab exercises on the processor aids considerably to the student's understanding of the lecture topics.